1. Field of the Invention
The present invention relates to a constant current circuit.
2. Description of the Related Art
FIG. 3 shows an example of a conventional constant current circuit (e.g., see FIG. 1 of Japanese Patent Publication No. 3423634). For example, the constant current circuit is employed for a circuit that generates a reference current of a variable gain amplifier (e.g., see Japanese Patent Application Laid-Open Publication No. 2004-120306).
A node OUT1 is a node between an output of an operational amplifier 13 and a gate electrode of an N-MOS transistor N6; a node out2 is a node between a resistance element R2 and a drain electrode of the N-MOS transistor N6; and a node OUT3 is a node between a drain electrode of a P-MOS transistor P5 and a resistance element R3.
An input voltage VIN is applied from an input terminal IN to a noninverting input terminal (+) of the operational amplifier 13, and a node voltage VOUT3 at the node OUT3 is applied to an inverting input terminal (−) thereof. An output voltage of the operational amplifier 13, that is, a node voltage VOUT 1 at the node OUT 1 is applied to the gate electrode of the N-MOS transistor N6. A power supply voltage VDD is applied to the source electrodes of the P-MOS transistors P5, P6, and a node voltage VOUT2 at the node OUT2 is applied to the gate electrodes thereof. The node voltage VOUT3 is applied to the drain electrode of the P-MOS transistor P5. The power supply voltage VDD is supplied to one terminal of the resistance element R2, and the node voltage VOUT2 is applied to the other terminal. The node voltage VOUT2 is applied to the drain electrode of the N-MOS transistor N6, and a ground voltage VSS is applied to the source electrode thereof.
In the above configuration, the operational amplifier 13 compares the input voltage VIN and the node voltage VOUT3 and applies the output voltage (node voltage VOUT1) corresponding to the difference to the gate electrode of the N-MOS transistor N6. The N-MOS transistor N6 sends a drain current Id corresponding to a gate-source voltage Vgs to the resistance element R2 so that a voltage drop occurs in the resistance element R2 (=R2×Id). As a result, the node voltage VOUT2 is developed at the node OUT2.
The node voltage VOUT2 is applied to the gate electrode of the P-MOS transistor P5. Therefore, P-MOS transistor P5 sends the drain current Id corresponding to the gate-source voltage Vgs to the resistance element R3 so that a voltage drop occurs in the resistance element R3 (=R3×Id). As a result, the node voltage VOUT3 is developed at the node OUT3, which is feed back to the inverting input terminal (−) of the operational amplifier 13.
The conventional constant current circuit shown in FIG. 3 uses the above series of operations to adjust the input voltage VIN and the node voltage VOUT3 to the same level. Since the gate electrode and the drain electrode can be controlled independently in the P-MOS transistors P5, the drain current thereof and the voltage drop in the resistance element R3 are not restrained. Therefore, as shown in FIG. 4, as the level of the input voltage VIN is increased, the level of the node voltage VOUT2 regulated by the voltage drop in the resistance element R2 is continuously reduced and, conversely, the level of the node voltage VOUT3 regulated by the voltage drop in the resistance element R3 is continuously increased. In this way, the voltage setting range of the input voltage VIN is equal to the operable range of the operational amplifier 13 and it is considered that a wide input voltage setting range can be ensured.
By the way, the present inventor has carried out a circuit simulation to validate operation of a constant current circuit 200 shown in FIG. 5 corresponding to the conventional constant current circuit shown in FIG. 3. FIGS. 6A and 6B show results of the simulation.
A differential amplifier 20 of the constant current circuit 200 shown in FIG. 5 corresponds to the operational amplifier 13, and a bias block 10 develops a bias for driving each transistor of a subsequent circuit such as the differential amplifier 20. An output current generating unit 30 is constituted by the resistance element R2 connected to the drain electrode of the N-MOS transistor N6 and the P-MOS transistors P5, P6 where the voltage drop in the resistance element R2 is applied to the gate electrodes and generates an output current Iout, which is a drain current of the P-MOS transistor P6. In a feedback voltage conversion block 60, the resistance element R3 is connected to the drain electrode of the P-MOS transistor P5, and the node voltage VOUT3 (feedback voltage) at the connecting potion thereof, i.e., the node OUT3 is fed back to the gate electrode of the N-MOS transistor N2 corresponding to the inverting input terminal of the operational amplifier 13.
FIG. 6A shows response waveforms of the node voltages VIN1 to 3 for the input voltage VIN and FIG. 6B shows a response waveform of the output current IOUT output from the output terminal OUT for the input voltage VIN.
As shown in FIG. 6A, when the input voltage VIN exceeds a predetermined threshold (when the input voltage VIN is near 0.90 V in the case of FIGS. 6A and 6B), The node voltages VOUT2, VOUT3 show characteristics that change electric potentials drastically and it can be seen that a linear control response as shown in FIG. 4 is not developed for the input voltage VIN. It can also be seen that the node voltage VOUT1 has a nonlinear control response as well. As a result, it can obviously be seen that the output current IOUT has a nonlinear control response as well.
The N-MOS transistor N6 and the P-MOS transistor P5 constitute a so-called two-stage amplification circuit and the input voltage and output voltage thereof are the node voltage VOUT1 and the node voltage VOUT3, respectively. This means that a high-gain two-stage amplification circuit is included in the feedback path of the differential amplifier 20. In the so-called Bode diagram, as a gain is increased, a phase margin (an index of how much margin exists until a phase becomes −180 degrees when a gain is 0 db) becomes insufficient correspondingly and, therefore, the output of the differential amplifier 20 may be oscillated unless appropriate phase compensation is performed.
In the countermeasures for avoiding the oscillation of the output of the differential amplifier 20, each gain of the N-MOS transistor N6 and the P-MOS transistor P5, i.e., each mutual conductance gm (a transfer characteristic indicating a relationship of the output current and the input voltage) may be reduced. The mutual conductance gm is generally expressed by the following equation (1). To reduce each gm of the N-MOS transistor N6 and the P-MOS transistor P5, each transistor size ratio (W/L) must be reduced.gm=ΔId/ΔVgs=(W/L)·μn·Cox·Vd  (1)                where L is a channel length; W is a channel width; Id is a drain current; μn is a mobility; Vgs is a gate-source voltage; and Cox is an electrostatic capacity of an oxide film.        
For example, if the channel length L of each transistor is increased to reduce the transistor size ratio (W/L) of the N-MOS transistor N6 and the P-MOS transistor P5, the level must be increased in return in the gate voltage that should be applied to each gate electrode of the N-MOS transistor N6 and the P-MOS transistor P5. To increase the level of the gate voltage, the level of the power supply voltage VDD must be increased correspondingly. If each gm of the N-MOS transistor N6 and the P-MOS transistor P5 is reduced in this way, a high-level operational voltage is required for each transistor correspondingly and it may be problematic that the circuit does not operates unless the level of the power supply voltage VDD is also high. Operating a circuit built into an electronic device with a lower power supply voltage is the demands of the times not exclusively to the constant current circuit.
In the countermeasures for avoiding the oscillation of the output of the differential amplifier 20, the gain of the differential amplifier 20 itself may be reduced. In the constant current circuit 200 shown in FIG. 5, the resistance elements R4, R5 are disposed on the source electrode sides of a pair of the N-MOS transistors (N1, N2). However, since the resistance elements R4, R5 are disposed, the offset of the output of the differential amplifier 20 is increased by the voltages of the both ends of the resistance elements R4, R5, and the correction ability against the difference between two inputs is deteriorated in the differential amplifier 20. As the offset is increased, it becomes difficult to make the finally acquired output current IOUT of the output terminal OUT consistent with a predetermined set current. If the gain of the differential amplifier 20 itself is reduced by disposing the resistance elements R4, R5, the two-stage amplification circuit of the N-MOS transistor N6 and the P-MOS transistor P5 has the gain exceeding at least “1(0 dB)”, the phase margin still tends to be insufficient. Therefore, if a parasitic capacity on the order of a few femto- to few tens of femto-farads (F) exists between the output of the differential amplifier 20 and the feedback input thereof, it is problematic that the oscillation may be induced.